The present invention generally relates to PCI Express (PCIe) technology, and in particular a PCIe bus extension system and method for adapting PCIe technology to current and future computer systems.
PCIe, formerly known as 3rd generation I/O (3GIO), has replaced the former peripheral component interconnect (PCI) parallel multi-drop bus as the main interconnect within current computer systems. In contrast to PCI, PCIe uses multiple lanes in parallel for each link, wherein each link constitutes a serial point-to-point connection comprising differential pairs for sending and receiving data in full duplex mode.
The currently prevalent PCIe 2.x standard features 500 MB/sec bandwidth per differential pair. In a PCIe 8x configuration (eight lanes), this results in a maximum of 8 GBs data transfers using concurrent send and receive transactions. The bandwidth of each PCIe link may be linearly scaled by adding signal pairs into a multi-lane configuration that can be custom tailored to the target (peripheral) device. Likewise, a multi-lane link may be split into several different targets. The width of each link or sub-link is negotiated at the initialization of each peripheral. At the end-point, the data that can be viewed as a byte stream are assembled/disassembled into the different lanes by the physical layer.
Given the high bandwidth and flexibility of the PCIe as an interconnect, it appears an unnecessary limitation to confine target devices to the physical location of an expansion card that is inserted into a PCIe slot of a computer. Rather, given space constraints as well as power and thermal management concerns, it would be advantageous to have target devices moved away from the motherboard and provide a high speed data link (HSDL) via dedicated cabling between an adapter card and the peripheral target device. U.S. Published Patent Application No. 2008/0244141 shows such a configuration using a dedicated PCIe expansion cable in pass-through mode. Likewise, a dedicated PCIe cable form factor has been defined by the PCI Express Special Interest Group (PCIeSIG) to allow creation of easy to install PCIe devices without limitations by form factor constraints. In either case, the cable receptacle is either a dedicated port on the motherboard requiring potentially costly redesign of the motherboard, or the interface is located on a dedicated expansion card to facilitate the integration of the PCIe cable. However, in order to satisfy electrical specifications, including length to connect to peripheral devices at a substantial distance (up to 25 ft (8 meters)) from the host system, the cable itself requires a bulky design which adds undesirable cost.
In view of the above, PCIe devices in their current form, including the integration of all components and necessary cooling, as for example in the case of graphics cards, are limited by rigid design specifications. These constraints, including thermal and power envelope as well as space requirements, complicate the ability to provide flexible implementations of devices that connect to a computer system through a PCIe interface. As such, it would be desirable to enable functional interfacing of a PCIe device with a PCIe bus, but allowing for the device to be located remote from the PCIe interface on the motherboard, and more preferably without the requirement that the device occupies internal space within the computer enclosure.